# CXMT Says Sixth-Generation 4F² DRAM Platform Passed Engineering-Sample Validation By Simon Yoon Canonical URL: https://www.tokenpost.com/news/technology/46139 Published: 2026-11-02T04:26:38.000Z Updated: 2026-11-02T04:26:38.000Z Section: Technology > CXMT targets first customer samples by year-end for a DDR5 RDIMM server module that pairs 4F² with hybrid bonding. ChangXin Memory Technologies (CXMT) says its sixth-generation DRAM platform built around 4F² cell architecture passed engineering-sample validation, moving the Chinese maker closer to customer sampling of a server-memory product planned for year-end. CXMT is targeting the end of 2026 to send customers its first product samples. The proposed module is a DDR5 RDIMM for servers that pairs the cell design with hybrid bonding. The company says a production ramp will depend on buyer testing and market demand. In DRAM, the notation captures the cell-layout area factor: CXMT aims to move it from six to four, allowing more memory cells in a fixed chip area. Its design uses vertically surrounding-gate transistors, and CXMT says it has more than 300 publicly disclosed patent families. The company also says its design can increase density at dimensions reachable through deep ultraviolet (DUV) lithography. Micron takes the opposite view on whether the architecture can scale. Scott DeBoer, Micron's president and chief technology and product officer, said the company plans to stay with its 6F² design before moving to 3D DRAM. DeBoer said Micron has examined 4F² for more than 20 years and sees no viable way to scale it, describing some discussion of the design as a smokescreen. Micron's technical argument centers on capacitor spacing and size, which it considers central limits on DRAM density. CXMT said architecture decisions also involve process-integration complexity, lithography steps and thermal limits. It added that companies weigh those factors against differences in technical history, production lines, patent positions and capital spending. Samsung showed a 16-gigabit 4F² prototype at the 2026 International Solid-State Circuits Conference and plans to use the architecture at nodes 10a, 10b and 10c before switching to 3D DRAM at 10d. SK hynix validated read and write operations on a test array in July and plans to present research on capacitorless 4F² technology at the International Electron Devices Meeting in December. The development builds on [CXMT's plan for a 4F² server-memory launch by year-end]() and adds a validation milestone ahead of the targeted customer samples. ## Links in this article - [CXMT's plan for a 4F² server-memory launch by year-end](https://www.tokenpost.com/news/technology/30865)