Nagare Labs Raises $5 Million to Develop Its AI Memory Design

Nagare Labs emerged from stealth Oct. 26 with $5 million in funding led by Playground Global to develop a memory design for artificial intelligence (AI) chips. Former Intel CEO Pat Gelsinger, a Playground Global general partner, is listed as a director on Nagare’s board. The startup says its current work remains at the lab-prototype stage.

Nagare’s proposed Z2RAM design uses oxide-semiconductor transistors to stack memory above an AI accelerator. The arrangement is intended to put more memory near the circuits that use it. Fast memory close to a processor can consume valuable chip area, while higher-capacity memory farther away adds data-transfer costs. Nagare’s design aims to address that placement trade-off by putting memory layers above the accelerator.

The company projects that its first design, with six memory layers, could deliver five times the bit density of two-nanometer high-density SRAM. The figure comes from a layout simulation and is a design projection, not a result measured on a commercial product. Gelsinger said the design “operates on existing fab infrastructure.”

Nagare was co-founded by Georgia Tech researchers Suman Datta and Shimeng Yu. Datta described the company’s current work as “literally lab prototypes.” The startup is seeking a fabrication partner and aims to sample working memory tiles within four years of Oct. 26, 2026. It targets production shipments within 10 years; both milestones are goals, not scheduled deliveries.

Integration is another development challenge. No standard currently governs how the proposed memory would connect to an AI accelerator. Nagare’s density projection and ability to manufacture the design at product scale have yet to be demonstrated beyond the lab.

Nagare’s announcement was distributed at 9 a.m. ET (1 p.m. UTC) on Oct. 26. The company’s next stated step is to find a fabrication partner as it works toward its memory-tile sampling target.