日月光 Targets Initial Volume Production for AMD Venice in Q1 2027

Panel-level packaging for AMD’s Venice CPU targets initial volume production in Q1 2027, with output potentially limited, as Taiwan’s Ministry of Economic Affairs investment review committee approved 力成’s $400 million investment in a Singapore venture.

日月光 and its subsidiary 矽品 are working with AMD on second-generation fan-out embedded bridge (FOEB) packaging for the CPU. Initial volume production is targeted for Q1 2027, with the first run potentially limited.

Panel-level packaging (PLP) uses large square panels instead of circular wafers. For Venice, the interposer is 2.7 times the size of a photomask reticle. After accounting for edge losses, a 310-by-310-millimeter panel can fit 25 interposers, compared with 22 on a 300-millimeter wafer, yielding about 14% more per panel than per wafer.

The difference grows in a 9.5-reticle example: a panel can fit nine interposers, compared with four on a wafer. Moving to that larger format depends on more mature equipment. Panel warping, process uniformity, alignment and yield also remain challenges.

Separately, Taiwan’s Ministry of Economic Affairs investment review committee approved 力成’s $400 million investment to establish XCIP TECHNOLOGIES with Broadcom in Singapore on Oct. 28. The venture’s planned services include panel-level advanced packaging, assembly and final testing.