AMD and Qblox Build Quantum Error-Correction Link With 0.44-Microsecond Latency

AMD and Qblox are developing a quantum-classical connection with an approximately 0.44-microsecond data-transfer round trip between the control system and classical computing hardware. The collaboration focuses on moving measurement data from a quantum control system to classical computing hardware and sending a response back.

Error correction involves a sequence of measurement, classical decoding and response. Qblox’s synchronized control and readout modules coordinate circuit runs and capture qubit measurements. FPGA-based modules handle work within that control stack, while classical processors run the error-correction algorithms. The new connection addresses the handoff between the control system and the classical compute hardware.

The link joins Qblox’s modular Cluster system to an AMD Alveo™ U55C link card. Four Aurora lanes carry data, each at 10.3125 gigabits per second. The Aurora plug-in packages incoming frames as 512-bit words at 250 MHz, then transfers them directly to accelerator memory through PCIe peer-to-peer writes. Replies travel back through a similar route.

The request queue is held in accelerator memory, while the reply queue sits in the FPGA. That arrangement supports polling at both ends of the connection. The full round trip takes about 0.44 microseconds.

AMD’s compute hardware options for the framework include Adaptive SoCs, FPGAs, Instinct™ GPUs and EPYC™ server CPUs. Decoders can run on FPGAs, CPUs or GPUs within the same framework, giving developers several hardware options for processing measurement data. Supported programming models include Python, C, OpenMP and GPU kernel chains.

The physical link is modular, so it can be replaced or upgraded without changing higher layers of the system. The runtime is also designed to support calibration, telemetry and adaptive measurement in addition to quantum error correction.