Samsung Prepares HBM4E Cooling for Larger AI Interposers

Samsung Electronics is preparing multiple cooling technologies for next-generation high-bandwidth memory as AI packages place more compute chiplets and memory stacks on single interposers.

Interposers connecting processors with HBM could expand from about 5.5 times the 858-square-millimeter maximum exposure area of an extreme ultraviolet lithography tool to roughly 40 times that size. The larger structures are increasing the need for more effective heat management.

The projected growth reflects limits on process scaling and the wider use of chiplet-based 2.5D packaging. Multiple compute chiplets and HBM stacks are being placed on one interposer because a single advanced-process chip may not provide enough AI computing capacity.

Samsung plans to begin mass-producing HBM4E in 2027 and is evaluating several ways to manage heat in the larger packages.

One approach is hybrid copper bonding, which directly connects copper surfaces instead of using microbumps between stacked DRAM dies. The design can narrow the gap between layers, produce a thinner stack and improve heat dissipation. Samsung displayed the technology at NVIDIA’s GTC conference in March 2026.

Samsung is also validating a thermal-path block with HBM4E. The structure creates a dedicated route for heat around the D2D PHY area of the HBM base die, where the die handles high-speed data transmission with the GPU. Samsung plans to introduce the technology with HBM5.

Interposer sizes are expected to increase in stages, reaching about nine times and 12 times the maximum EUV exposure area before potentially expanding to roughly 40 times that size as one package incorporates more compute chiplets and HBM stacks.