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Samsung to Use TSMC’s 3-Nanometer Process for Nvidia’s NVHBM Base Dies

Nvidia’s specifications also call for 1c DRAM core dies at Samsung, SK hynix and Micron, while Samsung’s standard HBM4 and HBM4E use its own 4-nanometer base-die process.

A silicon wafer beside a layered stack of memory dies / TokenPost.ai
A silicon wafer beside a layered stack of memory dies / TokenPost.ai

Samsung Electronics plans to use a 3-nanometer process from Taiwan Semiconductor Manufacturing Co. (TSMC) for the logic base die in Nvidia’s custom NVHBM, bringing an outside foundry into one part of its memory production.

Nvidia has set shared manufacturing specifications for Samsung, SK hynix and Micron. The base dies are to use TSMC’s 3-nanometer process, while the core dies that store data are to use sixth-generation 1c DRAM. The base die handles logic functions.

Samsung’s foundry division accepted Nvidia’s terms after an internal review. The shared specifications are intended to support consistent performance across suppliers and reduce the work required to validate each supplier’s product.

Nvidia introduced NVHBM in August 2026. The custom product is based on HBM4E, the seventh generation of the high-bandwidth memory standard.

Samsung’s standard HBM4 and HBM4E use its own 4-nanometer process for base dies. Their core dies are produced on 1c lines in Hwaseong and Pyeongtaek. Samsung also plans to keep its in-house production approach for custom HBM supplied to AMD and other customers.

Samsung is checking whether its foundries can make NVHBM base dies as a backup if demand exceeds TSMC’s capacity.

Simon Yoon

Reporter

Simon Yoon reports on blockchain technology for TokenPost. Send corrections or tips to info@tokenpost.com.

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