Cadence Plans Q4 Early Access for Maestro Chip-Design AI Models

Cadence introduced Maestro on Monday, Oct. 26, a portfolio of specialized AI models for chip and system design agents. The first models are expected to reach select early-access customers in the fourth quarter of 2026.

Maestro is a model layer for Cadence’s AI Super Agents, which work with the company’s electronic design automation and system design automation tools. It combines post-trained, domain-specialized language models for chip design with trained decision models and agent skills. The portfolio is designed to work alongside frontier and open-weight models. Cadence lists AuraStack, ChipStack, InnoStack and ViraStack among the agents that can work with Maestro.

Initial workflow results showed up to 30% higher “quality of results” and up to five times greater token efficiency than a general-purpose foundation model.

Maestro includes NVIDIA Nemotron and can be post-trained on customer data, designs and workflows. Its agentic environment can run in Cadence’s cloud, public clouds or customer-controlled on-premises environments. Cadence and NVIDIA are also working on agent security through integration with NVIDIA’s OpenShell Reference Architecture.

“Agentic chip design requires AI that can generate design content, evaluate tradeoffs and learn from verified engineering results,” Tim Costa, NVIDIA’s vice president and general manager of industrial and computational engineering, said.

Synopsys and OpenAI announced a multi-year agreement on Sept. 30 to develop GPT-Synopsys, a specialized chip-design model planned to run on OpenAI-hosted infrastructure. Cadence’s stated deployment options also include customer-controlled, on-premises environments.

Cadence announced a new RTL Generation Agent for ChipStack on Sept. 22, with select-customer early access also expected in the fourth quarter of 2026.