Samsung Targets Early 2027 Completion for 3D Cube-H Development

Samsung Electronics plans to complete development of its 3D Cube-H chip-packaging technology and a first design kit in early 2027, advancing an approach aimed at high-performance AI semiconductors.

Cube-H uses hybrid bonding to stack chips vertically. Samsung is advancing the technology with terminal spacing of about 6 microns. Its earlier 3D Cube-T uses thermocompression bonding, while thermocompression-bonded chips have a minimum terminal spacing of about 25 microns.

Hybrid bonding joins copper across chip interfaces, allowing closer terminal spacing and denser connections while reducing energy use per bit. Its heat dissipation characteristics differ from those of thermocompression bonding.

Cube-H could stack logic chips such as GPUs or combine a logic chip with memory such as HBM. Samsung plans to begin evaluations with potential customers after development and the first design kit are complete.