Cognichip Says AI Model Cut Front-End Chip-Design Work From Months to Days

Cognichip says its Artificial Chip Intelligence model helped one engineer finish front-end design tasks based on a 55-page specification in days, a process that typically takes a team four to five months.

ACI is Cognichip’s foundation model for semiconductor work. The front end turns written requirements into a chip’s logical structure before physical implementation. Cognichip designed ACI for two chip categories: application-specific integrated circuits (ASICs), built for particular tasks, and field-programmable gate arrays (FPGAs), which can be reconfigured after they are made.

The company also points to demo results showing an 18% reduction in leakage power and timing closure at 2.4 GHz. Leakage power is the power transistors consume while idle. Timing closure means the design meets its timing requirements at the specified clock rate.

At advanced process nodes, one tape-out — sending a completed design to manufacturing — can cost $40 million to $100 million. Chip-design cycles can also span several years, making faster early-stage work a potential way to ease some of the pressure on design teams.

Cognichip projects a shortage of more than 1 million chip designers by 2030. The company says its approach could help the industry design two to three times more chips annually.

Cognichip says it is working with more than 40 companies, including chipmaker Renesas and timing-device company SiTime. Founded in mid-2024, the startup emerged from stealth in 2025 and has raised $93 million. Its largest round was a $60 million Series A in April 2026, led by Seligman Ventures, with Lux Capital and Mayfield among the participants.

Other efforts are applying AI to semiconductor engineering. Nvidia and ChipAgents are expanding work on AI tools for chip design and verification, while Cognichip says ACI is designed for both ASIC and FPGA workflows.