AMD Completes Panel-Level EFB Validation and Targets 2027 CPU Production

AMD and 力成 completed validation of panel-level elevated fan-out bridge (EFB) interconnects as AMD outlined a broader server CPU roadmap targeting volume production in 2027.

Venice will use TSMC’s 2-nanometer N2 process with CoWoS-L advanced packaging and EFB connections. AMD server architecture head Mahesh Subramony said the short connections are designed to reduce power use and latency as processors add cores and move more data between dies. Verano will use TSMC’s N2P process.

Separately, 日月光 and 矽品 are participating in development and validation of wafer-level 2.5D bridge interconnects. A related Venice panel-level packaging effort had a Q1 2027 initial volume-production target.

AMD projects the data center CPU market will grow from about $26 billion in 2025 to about $220 billion in 2030, a compound annual growth rate above 50%. In May 2026, AMD announced plans to invest more than $10 billion in Taiwan’s industry ecosystem to expand strategic partnerships and advanced packaging capacity.

The Venice SP7 platform has shipped. AMD expects its enterprise-focused SP8 platform to become available in the first half of 2027, with Verano and Venice-X scheduled for the second half.